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- Design Solutions Overview
Our library of communications and signal processing IP cores and solutions include
- Flexible, efficient multiplexing / demultiplexing
- FEC encoding / decoding (Reed-Solomon, Trellis, Viterbi)
- Fast scrambling / descrambling
- Pulse shaping
- Equalization (FFE, DFE)
- AGC
- Acquisition and tracking algorithms
- UARTs
- SPI and other serial protocols
- Programmable digital filters
- Phase-noise and phase-hit mitigation for complex waveforms
- Efficient DFT's
- Block and bit interleaving
- Clock recovery
- IQ recovery and resampling
Satellite Applications
Satcom IP Modem
Satcom IP Modem
- Space terminal for 10 Mbps full-duplex IP packet-based ground-space link
- QPSK modem, Reed-Solomon codec, and packet processing implemented in triple redundant Xilinx V4 FPGA array
- cPCI interface for network packet flow to/from PowerPC
- Signal processing VHDL and supporting Linux network driver
- GUI test environment / framework
- Command and telemetry GUI
- Satcom IP Ground Terminals
Satcom IP Ground Terminals
- Ground terminals for Satcom IP Modem (above)
- Single-chip implementation in Altera Cyclone II FPGA
- Complete, managed ground terminal
- Analog I/O Engineering Model
Analog I/O Engineering Model
- Hardware design and verification for flight Engineering Model
- Multiple channel ADC (3x 93.3 Msps)
- Multiple channel DAC (3x 373.3 Msps)
- 2.5 Gbps SERDES, synthesizers, clock distribution, analog filtering, cPCI interface
- Built-in Self Test capability in FPGA
- GUI test environment / framework
- GPS Digital Synchronous Detector
GPS Digital Synchronous Detector
- Digital processing loop for high-precision Rubidium clock physics package used as timing reference for GPS satellite
- Algorithm development and proof of concept
- Algorithm implementation, ADC and DAC interfaces, command and control
- Implemented in commercial and path-to-flight hardware
- Baseband Beacon Generator
Baseband Beacon Generator
- Walsh-code sequence generator and pulse shaper for BPSK modulated satellite beacon
- Root-raised cosine filter, DAC, and synthesizer control
- Prototype for flight design
- Implemented in Actel FPGA
- Terrastar Synthesizer Interface Controller
Terrastar Synthesizer Interface Controller
- Command and telemetry interface for flight synthesizer
- Loral M-500 bus protocol interface module
- RS-485 transceivers and UART
- Prototype for flight design
- Implemented in Actel FPGA
Terrestrial Communication Applications
Gigaband Digital Receiver and Demodulator
Gigaband Digital Receiver and Demodulator
- Multi-mode demodulator: BPSK, MSK, (O)QPSK, 8-PSK, 16-APSK, 32APSK
- Symbol rates from 1 to 600 Msym/sec provides 3 Gbps throughput
- Vector-based signal processing algorithms
- Chip-to-chip transfer rates > 30 Gbps
- 2.5 Gsps ADC + (4) Virtex-4 LX160s
- Spitfire Multi-Channel CDMA Modem
Spitfire Multi-Channel CDMA Modem
- System architecture and waveform definition for BWA system
- CPE modem implementation using Xilinx Virtex IIE FPGA board
Other Applications
Whispercode Voice-band Processor
Whispercode Voice-band Processor
- Digital watermarking system for analog broadcast television
- Algorithm implemented in TMS320C6211 DSP
- Development and license of set-top box
- >10K produced; currently in multi-city field trials
- Production Test Executive
Production Test Executive
- Technician interface for automated test
- Graphic/picture driven Test-Procedure instructions
- Extensive log files with XML data options
- Ability to run subtests in "troubleshooting mode"
- Development GUI
Development GUI
- User Interface for performance evaluation and equipment configuration
- Hardware access over USB, Ethernet, and serial interfaces
- Quasi-real time performance evaluation via snapshot/playback buffers embedded into digital logic under test
- Flexible graphing of signals: time-domain, frequency-domain, and constellations (modulated signals)
